The present invention relates to structural improvements for lower power dissipation of peripheral equipment for use with workstations and personal computers. More particularly, the invention relates to structural improvements for lower power dissipation of semiconductor integrated circuits within peripheral equipment control devices.
Heretofore, various proposals have been made to reduce power dissipation not only in peripheral equipment for workstations and personal computers but also in LSI's (large scale integrated circuits) for control over such equipment.
For a first prior art example, take some peripheral control LSI's having an input terminal dedicated to specify low power dissipation mode. Receiving signals from an external microprocessor or a power dissipation controller through such dedicated terminal, this type of LSI maintains low power dissipation mode during designated periods. That is, part or all of the clock pulses are stopped during designated periods for those digital circuits in a peripheral control LSI which operate on a reference clock signal. The result is a reduced level of power dissipation. In another arrangement, the power from a current source circuit is also cut off to part or all of the analog circuits in the peripheral control LSI during designated periods. This further lowers the power dissipation involved.
For a second prior art example, take such peripheral equipment as a hard disk unit, CD ROM (compact disk read only memory) or floppy disk unit which may be constructed for reduced power dissipation with smaller size and less weight. As described in the Product Specification of Small Hard Disk Drive DRR040C (first edition) issued by Alps Electric Co., Ltd., the above construction involves having the peripheral equipment receive commands from a host computer (microprocessor, etc.) and execute them only then so designated.
FIG. 18 schematically shows the DRR040C as typical prior art peripheral equipment. The DRR040C comprises disks 1801 which are magnetic media; heads 1802 that read magnetically recorded information from the disks 1801; a head actuator 1803 that moves the heads 1802 to a target position on the disks 1801; a spindle motor 1804 that rotates the disks 1801; an actuator control circuit 1805 that controls the operation of the head actuator 1803; a CPU (central processing unit) 1806 that controls the whole operation of the DRR040C; a spindle motor control circuit 1807 that controls the spindle motor 1804 in accordance with control signals from the CPU 1806; a digital-to-analog converter 1808 that converts to analog format the digital information coming from the CPU 1806 and forwards the converted information to the actuator control circuit 1805; a read/write circuit 1810 that shapes into a waveform the signal read from the heads 1802 for conversion to a pulse train; hard disk controller 1811 that converts to parallel data the pulse train generated by the read/write circuit 1810; an analog-to-digital converter 1809 that converts to digital format the head position and other analog information detected by the read/write circuit 1810 and sends the converted information to the CPU 1806; a buffer 1813 that temporarily accommodates signals from the disks 1801 or from an AT bus 1812 in order to adjust the difference in read rate between the AT bus 1812 and the disks 1801; and an AT bus control circuit 1814 that controls the AT bus 1812 under direction of the CPU 1806. It is to be noted that the AT bus is a bus having the PT/AT (a registered trademark of International Business Machines Corp.) Interface.
When not receiving or executing a command from the AT bus, the DRR040C operates as follows so as to reduce power dissipation:
1. When the command from the AT bus is complete, the DRR040C enters idle mode (1). In idle mode (1) , the CPU 1806 of the DRR040C stops the hard disk controller 1811 and cuts off power to the read/write circuit 1810. PA1 2. If not accessed from the AT bus within 5 seconds after entering idle mode (1), the DRR040C enters idle mode (2). In idle mode (2), the CPU 1806 of the DRR040C cuts off power to the actuator control circuit 1805, to the digital-to-analog converter 1808 and to the analog-to-digital converter 1809. PA1 3. If not accessed from the AT bus within a certain period of time (default is 3 minutes) after entering idle mode (2), the DRR040C enters standby mode. In standby mode, the CPU 1806 of the DRR040C cuts off power to the spindle motor control circuit 1807 and the spindle motor 1804. The CPU 1806 also enters sleeping state. PA1 4. Upon receipt of a sleep command from the AT bus, the DRR040C enters sleep mode, which is a fully low power dissipation mode. On entering sleep mode, DRR040C causes the AT bus control circuit 1814 to leave standby mode and to enter sleeping state. In sleep mode, the DRR040C accepts no commands from the AT bus; only a reset can activate the drive.
Operating in the manner described, the DRR040C reduces power dissipation when not receiving or executing commands from its host computer.
In the first prior art example, lower-power dissipation mode is designated by a microprocessor or controller external to the peripheral control LSI. This means that to implement minimum power dissipation requires the external microprocessor or its equivalent to issue a low power dissipation mode command a number of times. One disadvantage of this scheme is that the burden on the microprocessor tends to be too heavy.
In addition, the external microprocessor or its equivalent cannot grasp precisely what is taking place within the peripheral control LSI that designates low power dissipation. This is where another disadvantage of the scheme is recognized; the inability of the microprocessor accurately to grasp the internal LSI operations makes it impossible to control them in a delicate manner required to achieve minimum power dissipation.
In the second prior art example, there is no consideration for the current consumed by the AT bus control circuit 1814 in standby mode. This leaves room for an increase in power dissipation. In sleep mode, which is a fully low power dissipation mode, no commands are accepted; only a reset from the host computer or its equivalent activates the drive. This neglect for the responsive characteristic of the drive is liable to increase the overhead of the host computer.